This invention relates to a memory having a CMOS SRAM-cell, the cell including a pair of cross-coupled inverters, and each inverter having a series connection of an inverter-PMOS-transistor and an inverter-NMOS-transistor between two supply terminals for receiving a supply voltage thereon. Outputs of the inverters are coupled to respective bit lines via respective NMOS-access-transistors, and the memory includes precharging means for precharging the bit lines to a predetermined precharging voltage before executing a read-operation.
A memory as defined above is disclosed in an article in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987 entitled "A 40-ns/100 pF Low-Power Full-CMOS 256K (32K.times.8) SRAM" by W. C. H. Gubbels et al. This article discusses an advanced SRAM which is constructed by means of a 1.3 .mu.m process. Reliable transistors for a 5 V power supply are obtained using a lightly doped drain (LLD) structure for protecting the transistors against "hot electron stress". The hot-electron stress phenomenon is well-known per se, and is the result of charge carriers in the channel of the relevant transistor being accelerated by the source-to-drain electric field to sufficient energy to ionise the channel material on impact, so that valence band electrons of the channel material are excited into the conduction band. Each time such an event occurs the result is an extra conduction electron and a hole, which may flow to the drain and substrate respectively, giving rise to increased drain-source current and substrate current. If charge carriers generated by impact ionization have sufficient energy, they are able to surmount the energy barrier between the channel material and the insulating material for the transistor gate. Once in the insulating material some carriers become trapped, creating both fixed charge in the insulator and interface traps, which in turn give rise to a change in the transistor characteristics.
A present trend is a desire for memories having larger and larger storage capacities, and this implies a desire for a reduction in memory cell size in order that the larger number of cells required can be accommodated on a reasonably-sized area of substrate. A reduction in memory cell size entails a reduction in size of the constituent transistors of the cell. However, it has been found that if the channel lengths of the cell transistors are reduced to below 1 .mu.m (submicron), for example to 0.8 .mu.m while the operating conditions are maintained unchanged "hot-electron stress" occurs in the NMOS transistors in spite of using a lightly doped drain (LLD) structure for the transistors, resulting in a drastically reduced life expectancy for the cell. It will be evident that the hot-electron stress could be avoided if the voltages supplied to the cells were suitably reduced but it has been found that in general such reduction results in a considerable increase in the time required to access the cells. It is an object of the invention to mitigate this disadvantage.